A commonly used method for applying compressive stress to the channel regions of PMOS devices includes growing silicon germanium (SiGe) stressors in the source and drain regions. Such a method typically includes the steps of forming a gate stack on a silicon substrate, forming spacers on sidewalls of the gate stack, forming recesses in the silicon substrate and adjacent to the gate spacers, and epitaxially growing SiGe stressors in the recesses. An annealing is then performed. Since SiGe has a greater lattice constant than silicon, it expands after the annealing. The expanded SiGe stressors apply a compressive stress to the channel region of the respective MOS device, which is located between a source SiGe stressor and a drain SiGe stressor.
In the formation of the SiGe stressors, some metal elements such as iron, chromium, nickel, and the like, may be undesirably introduced into the SiGe stressors. The metal elements may come from the material of the chamber in which the SiGe stressors are grown. Following the formation of the SiGe stressors, source and drain regions are formed by performing a source and drain implantation. The source and drain implantation may cause the metal elements to be driven down into the substrate. The metal elements may aggregate to form clusters, which in turn cause the device performance tailing and the lowering of manufacturing yield.